dick_freebird
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Don't take my word for what's possible or practical. Only what I've seen, and what I'd like to see. I imagine that a smart guy could code up a script to perform a "masked select" and then it would be easy (I'm told) to add it to your pri…
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I take it that these are "post fab" RDL features, then? I worked at an RFIC company for a while, they used RDL copper for some products. The CAD group had to add these layers to the basic foundry layer set in order that the designers c…
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This is something I've been interested in. My thinking has more revolved around the selection process and how to make it "maskable". But this could take several forms. You could add a "lock position", "lock properties"…
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Not only will they be connected, but this layout would violate basic layout rules. Specifically, via must stop on metal below, else you will etch further into lower interlevel / field dielectric. You will have a fight on your hands, when you get to…
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When I say "baby Caliber", that's a limited version which was bundled with Tanner L-Edit. Later on a more capable (and much, much more expensive) version became part of the Mentor / Synopsys tools set, proved itself more capable of very l…
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I don't know about "big boy" Caliber, but I have been provided Caliber DRC output that's near human readable (if you like mangled English and raw coords / arbitrary device & node naming) from a foundry that uses the "Lite" …
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That's all the way to the bottom of the turtle-pond, yep. Turtles, turtles, turtles. Please post your work once you get it solved so the less (or not at all) clueful among us, can get some traction.
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OP mentions vaguely that there's already a method. What attempt so far, to replicate that method in the "custom device extractor" way? My points have been generally, that there is not a general agreement on even an always-rectilinear form…
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You'd first need to be able to assign terminals and figure a direction between them (L) and orthogonal (W). Same as a thin film resistor I expect. But capacitors I have seen (and drawn) tend to be direction agnostic - MIM caps are nothing but plat…
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If you're not modeling series R then it's a "don't care". Asking for W and L presumes a rectangular form. I am used to seeing "free-form" capacitors in analog IC design (older vintage) and I'd just be taking the thin oxide * top …
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I still don't see addressed, my question whether ".klayout/pymacros" (3rd post) is (1) normal / proper, (2) a valid search path entry. Might suggest trying to invoke these "missing" scripts by full path and see whether it's find…
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I can see value in a standalone, GDS-II DRC checker. However I imagine that the operation of DRC here, has to take advantage of the GDS-II layout loaded-database infrastructure, and to "bust out" the DRC you'd probably end up duplicatin…
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In the example, LVS should produce a layout device with no schematic match. So the problem would be caught. Does it matter -how- you catch an error? More than just time spent getting there (DRC precedes LVS usually)? I wonder whether what's need…
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Might start off with inspecting the (presumably) loaded DB and see whether it still contains multiple topcells. And be sure that those $args had predefined values that work; were there preceding error yips, about that?
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I'd guess that you have to find a DRC-only means of 1) finding same-named (or swappable, more fun) terminals of same-named devices, and put them in orderly lists 2) create some sort of polygon that represents a contiguous connection and "kno…
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Maybe your macro search path then needs to have ~/.klayout/pymacros included as well as the default .klayout? What happens if you move the Python scripts to ~/.klayout level?
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Not sure about the bit regarding "you need to define a Spice reader delegate to capture model subcircuits". To me, all that it wants is to spit out an "X" element card, rather than M/Q/D/R/C/? netlist lines. The subcircuit de…
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I think there may be another "layer" behind this - what of the case that the resistor's isolation is not "bulk" (i.e. the P- handle / epi) but some other isolation region like (say) a P+ resistor in NWell, or my above example of …
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Layer properties can be saved in .lyp and reloaded as-saved, at any time. Technology setup usually points at such a .lyp, but if you are saving by another means (the layer display details) maybe the technology save-as, only saves the .lyp file po…
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There is a "netgen" which performs any-to-any netlist compare. Not easy to find although it's part of the efabless / opencircuitdesign MAGIC-based toolchain (there are other "netgen" developments, newer and unrelated, which Boga…
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Or ^Z, though that might "undo" the whole command?
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I am still interested to see a "select mask" capability based on a layer / polygon. My thinkiing goes to the old Cadence behavior (seemingly broken in IC6 layout, but remaining in schematic / symbol editors) that keyed on the instance/dr…
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Is the data already local on that SSD? Or coming from some other source? I imagine that the load-rate could be dependent on other things such as media data rate (transferring from an older USB2.0 thumb drive at 10MBPS, or over a 10Mbps Ethernet bra…
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This doesn't look like the install / build instructions I followed the last time I built from source. I don't recognize 'build' command in all that. I recommend you find and follow the basic instructions, and look at the log for complaints about d…
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I tried something out. A multi-vertex polygon can have a single vertex selected by Partial tool: (Image) There you can see an "innie" vertex selected. Now if you delete that vertex, the shape becomes fully convex. So seems like, i…
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My impression is that the problem involves a convex shape, and vertex-snapping perhaps is making local concavities that become "notch" errors? I guess there "could" be logic that makes all vertex snapping "radially outwar…
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A cursory check's impressions: 1) Tight and pretty, more than just a html-stack "paste job". Prettier than anything I've done by hand. 2) Cross-links and index seem to work perfectly 3) Got to a "Classes" section which was all…
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I guess my first advice would be "Know your audience". Or audiences. Are you trying to document the PDK for users, maintainers, those who might build upon it elsewhere? All of these, some of these? And do you believe they all want the s…
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On the note of marker layers, you might like to take a dive into the mainstream foundry PDK (if this is meant to get real) and look for these kinds of layers ("capacitor/drawing"?) and also see if there's a multifinger MOM cap already dr…
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That's going to be tricker because it's a 3D problem (vertical and lateral fringing dominates). An extractor -could- handle it but whether this one does, I do not know. Would be some more elaborate code than a vertical only, plate-plate capacitance …