dick_freebird
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In my work I've built the layer tables by hand from paper sources, but haven't I seen that there's some facility to import Cadence techfile info? If there is, that'd be the easy way, presuming the foundry wants to talk to you. If there isn't, th…
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Freeze for how long? It might be stuck searching locations, or have a location in the search-path that is waiting to time out for not-found? Have you looked into what the search-path is, and inspected the current search-path string for stuff that i…
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I couldn't find the Change All function in my 0.26.8 installation, but I would simply use the "q" property editor on the selected set, make sure I had the pane for Center / Size (if rectangles) selected, change the attribute of interest i…
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If your klayout DRC runset equals the Cadence (or Caliber, as many "Cadence centric" foundries use Caliber as the golden tape-in tool) then the tape-in check should be a "nothing to see" event. But then somebody would have had…
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I would like to see, somewhere in the release collateral, a complete list of all packages required (with version) or better yet, some "pull scripts" that would ensure that the dependencies are all in place or make it so. Like apt for Ubun…
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I occasionally have to go back to the schematic and update the length and segments properties to reflect the "observed layout reality". This would be one of your your "local" options, appropriate if the schematic reflecting as-l…
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I would suggest that the default version be something more toward the "trailing edge" so that other tools and older versions can have a chance of working. What is the value of following Autodesk's deliberate version- churning too closely? …
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The solution may lie in the rules logic, like check that (topMet*silox)==145 as a pad specific rule, rather than looking for 150x150 metal alone, supplementing the more generic width/space check(s). The pad rule is really about the window, extra…
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Thanks, Matthias, I didn't get that "Auto" meant "Layer_Edge". Thought it was just "do what you want, klayout".
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I'll take this opportunity to advocate for a truly generic extractor. I would like to be able to arbitrarily define an arbitrary number of pins with arbitrary layer_logictext "pin recognizers" and a layer_logictext "type recognizer&q…
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Do any of the snap related settings in Editor Options or Setup affect this? Such as "snap to other objects", or setting the grid down to base DB unit? Figure you would not want off-grid points generated in any case.
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Thanks, Matthias - that was going to be my next question. The QT_AUTO_SCREEN_SCALE_FACTOR=1 seems to have worked nicely enough, the text is larger (enough) and the "dependent" texts underneath the layer toolbox headings no longer "…
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Would this be a .bashrc entry, or a klayoutrc entry?
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Another thought in the vein of debug-slicing-the-problem - I know there are settings for what/how the layertable is displayed - you can, or not, show names / numbers / etc. I notice in Matthias' latest, the layertable window is not displaying any l…
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I don't pretend to understand the X-Fab PDK delivery but this looks to me, not like a XML format - more like a MIME-encoded email attachment. I wonder if you're "trying too hard" (or just wrong) and ending up with something that's not …
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If the pads all have a common master then could you not just collect the origin X,Y and do (X2-X1), (Y2-Y1) origin-origin saving the least delta found, dumb-loop-sort-style? Pitch is center to center. Of course this might fall apart if you have a …
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I don't understand what "tab" means in this context but do observe that the minimum layers window width is the widest-field "name layer datatype" text. The Cells window seems not to have a displayed- width-driven minimum. If …
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From the cheap seats this looks like good stuff....
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The only ways I know are to use the Edit>Selection> Subtract, Others From First or Separate, First into (blah blah blah) (Image) However both of these break the path into polygons. I prefer "stick" routing (box or poly) anyhow a…
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I have a default .lyp asserted and autoload box checked, and opening two panels with two different layouts is not bothering my "adjunct windows" at all. Maybe you should post your working .lyp for inspection. Maybe uncheck the default-…
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DRC sometimes is given or allowed a tolerance value for "good enough", so that trivial rounding or math resolution error does not throw a bunch of errors for (say) 10.000 != 10.00000000000000000001; is this something that is "known …
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You might have to go at it backwards, like make a derived layer that is "not(grow(via, lonelinessCriterion))" (excuse the lack of syntax-clue) and then do a dimension check on all those "holes" looking for anything that's minim…
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@ Matthias You always have a helpful hint, if only people ask. But that is a "lagging function". So let me ask this - when is your "Klayout Verification Scripting for Dummies" book coming out? That being a different thing tha…
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Here's a pic of what I'm wanting to address. This is a TANK region which serves as collector for two NPNs (with distinct B, E regions, Es wired together), one lateral PNP and two distinct Pbase resistors. The LPNP "B", VNPN "C"…
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Reviewing the doc link, I am a bit confused. "For the resistor with bulk, the wire area is output on the "tW" terminal layer as the "W" terminal:" is all that the resistor_with_bulk section declares (w/ pic) but it is…
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Here's a blast from the past which talks about some windows (like Macro Development) doing a "focus grab" which then prevents a lot of things from working: https://www.klayout.de/forum/discussion/comment/1960#Comment_1960 Do you have an…
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To Tracy's (tagger5896) remark, the "Aero" theme seems to be Win10 default but is meddlesome and needy. I use a "custom" theme with all the dancing eggplants disabled, basic black background, etc. You might try stepping away …
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I believe two things want changed. The schematic SPICE netlister needs to be "harmonized" with whatever a "normal" layout might produce for extracted device netlist lines. It would add a lot of flexibility if you made all dev…
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I tried that before posting, I could not get the adjunct windows to "get stuck wide".
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I believe you can have resistors with or without a model (certainly, without; forget the syntax for invoking a model instead of the built-in primitive). It might be that the schematic netlister needs to be "educated" to get the format t…