dick_freebird
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(Quote) This concerns me. I've been bitten by this when using asymmetric MOS devices (e.g. drain-extended, no LDD on source). This behavior (IMO) should be configurable, or an asymmetric MOS extractor needed. And then -if- it is configurable, com…
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Not sure why you'd do this or how realistic you think it'll be (much of CD variation will be systematic, and some more of it involving proximity / edge-of-array effects). But if it were my problem, I think I'd first make a PCell for the square objec…
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I don't think the devices want or can be combined because they are not fully parallel. What this situation lacks is enablement of specific pin swapping (S=D). Now "combining" could be done -to- the netlist or by bookkeeping during the …
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I'm wondering whether this is "algorithmic" (and a bug) due to the high vertex count and long shrink dimension, causing "spurious projection" as the vertices might cross over each other when projected orthogonal to their flat?…
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That's one such. "Still fail" is not very informative. Same fail, new fail, ??? The "optimize" probably needs some specific form and direction....
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I would bet that the netlisting "template" can be found, probably as a property of the PSPICE symbol itself (but I am no PSPICE expert). Try pushing down the hierarchy looking for pin and property passing. The PSPICE output log may show …
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What is missing, is a compare rule that says S, D are swappable in searching for topology-match. I know I've seen this discussed but can't remember more. Or you could go change the schematic so it matches what's naturally found, but is there &quo…
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How about making a "cutter" object (say, by subtracting a circle of desired radius, from a square) and then using that "cutter" on the target object? Both using the "Subtract, Others from First" operation? All straig…
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I'll mention that I've seen multiple times, that what you get from a distro's package repository can be badly out of date, or subject to an installer which sets you up to fail (like if it wants to install via "snap", you get stuck into a…
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It might be useful for the proponents of various simulator netlist formats, to dig into their simulator's documentation and see about options. There may be SPICE compatibility settings that enforce more-standard formatting. If there are no good op…
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I don't know from "conda" but I've encountered problems with applications "built inside environment", then having serious limitations. In my case it was "snap" installations, which carry a constraint (aka "sandbox…
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It would be good if the LVS could tolerate dialect differences. It might be expedient to do this by some "compatibility setting" (ngspice has compatibility flags for some of the more popular commercial simulators, as well as some guidance …
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The "not matching" probably refers tho the net topology, not the net name. The LVS should work without named nets (though less quickly and poorer odds) and still say which ones match regardless of name. It would be a pretty demanding a…
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Using Perl, Python or in my case old timey shell / sed scripts to massage netlists for various reasons, is a very done thing. Whether it's optimizing parallel FETs / fingers into one single device, or removing extraneous characters, or even building…
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"$" in ngspice means "value of" when applied to a variable. Using the variable name bare, might result in the assignment of the variable name rather than the variable value. if Y=1 then set X = Y ends up setting X to "Y&q…
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In a software which shall not be named, "F3" pops a context menu which includes all of the modal options for the active command (like transforms, snaps, gravity and such for a move / copy / stretch). It can be tricky to get such a thing …
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This (the actual construction and connections between layers) is what I was getting at. I think that inspecting the cutaway and level-plot figures which must attend the layout data for the process, should lead to sensible layer-logic and connect-l…
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If I recall, there is more than one place that sets snap angle, pertaining to different things / actions? Maybe the Partial and the Move functions refer to different "templates"? Or, maybe some "lock angles" deal is what prevent…
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Do you suppose that you could write a little bit of "wrap-up" that tells the problems, their cause and their solution apiece? Clean example is fine, but ability to recognize what the errors / misbehaviors are trying to tell us, comes from…
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If you are running klayout on a Linux machine and looking at Windows hosted data, then there's a chance that the paths "look different" depending on where you sit. I have run into this using remote systems (like, I may have a client's Wi…
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Looks like you are in some kind of "managed" PC environment where the path you type, and the path it gets resolved to, differ. Question #1 - is the full path in the popup error window, a valid path to the .CIR file? Then if it is, it may…
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I don't understand this bit about making G be the B contact. Active is the B region. S, D and G sit atop parts of it. Maybe you just want to make PWell = Active andnot NWell and use that to identify the PWells. Contact to PWell is global Psub andnot…
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If you could sort the boxes (presumably squares, as rectangles would want to become ovals?) into "heaps" of like geometry, then you'd have to do the circle- figuring once per geom instead of once per object. If you took each of those squ…
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Basic JI NMOS may have no "Well". Common on older technologies that had only one (or no) VT implant. You might elect to make one, to give the generic extractor "something to chew on". And put it on a layer that you can stream …
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Well crafted SPICE models will give you different (subtly) outcomes from (say) a 100/0.18 and a (10)10/0.18 FET. Your verification ahould not ignore or obscure this if any analog matching interests are involved. Probably want to make this a "…
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Define your own special purpose layer in the .lyp, build it into the device layout(s) and use as you see fit?
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If you are using, and others will be using a PCell for this device, then building in "recognition features" is a way to get at this easily. And if you make the features a polygon (or a text) then they can ride along in the GDSII. For ex…
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I think you will need to explain more, about what this text format should contain / look like. Are you asking simply for a list of the layers used, or some text export of all the polygons on one (or all) layers, and would that be a full list-of-ver…
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There's a couple of things I think you will need to do. One, File>Load Layers selecting the .lyp file may be needed to "bring the new layers front and center". Have you gotten a clean-loading (if not necessarily as pretty as you'd lik…
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There is an option in the main File>Setup pile, that says whether to open for view or edit by default. (Image)