Maybe if every layer of the path-resolution was "bite
sized" as a shall variable, the user might find a way
do this abstraction.
Personally I like full hard paths nobody can mess
with, but I am not subject to CAD management
or its dic…
I'd take this a step further and maybe look at
making a "CAD administration for non-sysadmins"
cookbook. We all want to jump ahead to the fun,
but running the Zamboni first (and maybe at half
time) does improve the game-play.
If it spr…
When I imported a R12 .dxf file I got named
layers with no evident numbering? Tag-along
"technology" layers from last chip DB were
still there with names and numbers both.
I imagine there's utility for some script, that
could parse DXF f…
A script would have to be "taught" by someone
or something that "knows" the meaning of each
layerNum.
A skilled layout or design engineer would have
some amount of the required "gut". A PDK layer
table of course woul…
I sense that the question is about the cursor
itself and whether its movement can be made
"steppy".
I believe the cursor movement is a separate
thing from the behavior of objects being
moved or made, by it. Those commands are
subject …
Personally I use .png and TIFF is about as fat
as an image file can be. But I only do interactive.
That all seems orderly and works fine (though I
could ask for "persistent background image" to
not have to re-attach every time).
What I do…
It would be occasionally useful, if the Cells
window offered a right-click "print this puppy"
option (following the choice of display-form).
To copy-buffer or to chosen-file.
Seems to me that a literal, polygon for polygon
translation ought to be an option. I'd guess that
the problem is vectors that are "loose", with no
"bundle" to decide which merge and which do
not in subsequent steps?
Perhaps thi…
Does the install bundle not state which
dependencies and versions?
If not, then you should put that question to
the maintainers.
However the error I see, looks more like
maybe a PCell:code_pile sync / content
problem, it seems a bit of code h…
I am still very interested to get a "selectable extents"
feature, like the old Brand X instance/dwg layer used
to act. Trying to dead-hit the zero width instance origin
is tough and using full extents is its own kind of pain
once you get…
I think ideally the "recognition" and "extraction"
should be so "meta" that an arbitrary bundle of
polygons can map to an arbitrary device which
has bound to it an arbitrary netlisting format
template (name, nodes, mod…
Are you sure that a different element
(like JFET) wouldn't do?
Or something like BSIMSOI rigged for
fully depleted "bodyless" MOSFET?
Check out what the CMOS RF switch
people do.
I'll interject that some foundries have a "waiver process"
(Brand X has a PVS "waiver tool", it's lame). But you can
in some cases negotiate a "relaxation" if it's not a
"production mask" and semi-automate s…
I don't want to see anything "closed" or removed, even worse.
We have an endless stream of newbies and serious but unfamiliar adopters and even if a question is "answered" its nuances or follow-up ones may still want a home. And…
Off the cuff, I wonder whether there is a "please,
no more!" error-display-limit hard coded, or if you
are lucky some setting (I see such things in
simulators' options, "maxwarn", "maxerr" like.
Maybe there is a built…
If you have no technology defined and no .lyp loaded
(clean start) then streaming in your gds file would
import every found layer/purpose pair.
Now you can inspect for those "xic" layers, and you
could save the layers to a new .lyp for …
Looks to me like the topCell name is "TOP".
What happens if you edit it to be "inverter" in
the extracted netlist, or assert "--topcell=TOP"?
Perhaps the layout netlister allows you to
assert the topCell name, to get…
I believe this is the tip of a coming iceberg, "chiplet mania" is going to demand ability to have "multi-tech meta-PDKs" if bottom-to-top design of 2.5D ICs is going to be a thing (true 3D, you're gonna need that third dimension …
Pixels are inherently integer and therefore are going to end up toggling around rounding error.
Grain of sand or no grain of sand. Dust is with the wind.
Paths act funny in big-$ tools too. I much prefer 45'd and 90 hand drawn on-grid rectangles for my work. They stretch predictably and overlap clean.
Of course this is not digital mainstream, never was.
Paths can be drawn with properties that…
Are you merging for some reason?
Making it all into a single polygon with a huge vertex
count seems like inviting mishap. Especially when
working at non-45-integer-multiple, rounding error
(and lacking a finishing snap-to) might be the source
of …
<=0.42 may be a "dogbone" FET (contact plus
oversize AA =0.42 min?). If so then there is a
definite polygon-level "break" in the relation of
as, ad, ps, pd to W.
Now why the extractor couldn't just fork the
geometry math, i…
I know nothing about scripting but somehow
this doesn't look like it takes action to save the
revised / product layout. Or where does the
produced data end up? As part of the source
layout (as none is declared or opened)?
Does your layertable ha…
Some people really like the auto-place and flight lines. To me they're a half-a$$ed guess (placed only as neatly as schematic is drawn - if that - and then cluttered up). I know where each transistor belongs and how signal flow is, so what's an alg…
Still think this is rounding error residue / "DBU beat frequency" stacking up.
Does your source data have such a funky DBU initially?
If so then maybe you must first upscale DBU per distance to a least-common-multiple, rasterize tha…