I see 4 seconds for a Win10, 4 core Dell M4800.
This kind of drag-out might be from long or not-ideally-
ordered search paths; especially remotely hosted (or
remotely not-found) path branches may take time to
"fail out and proceed"?
There's also a mode in the C(opy) command which puts
you in "move" but I never can tell whether I'm in it or not.
This came about after requesting an "infix" bindkey mode
for copy and move. I would like to know if there's some
o…
This would be an improper use of "merge devices".
They are -not- the same device. They all have different
tolerances, as-shot values, tempcos.
You should represent them as they are laid out, in the
schematic. "Merging" is just…
I am still hoping that the bindkeys will someday be made
completely and arbitrarily overwritable (a bindkey save and
load to / from an external file). The "special" status of the
built-ins, I think is the root of the problem.
The command (as far as I have seen) only works on "flat"
data (or what's at the present level of hierarchy).
Are you trying to make "cutouts" which will be able to change
later by editing the polygon and array, and have the cuto…
I tried out simply removing the "// L-Edit..." lines from the report file as you noted, and the Marker Browser works like a champ.
I withdraw the request! (Image)
Hi, Matthias,
I can send you a full results file privately. I was reluctant to
ask for anything as ambitious as a full report browser /
reader (even getting able to mark and zoom-to a single
coord-bundle would be a major improvement). But if the
p…
I was rummaging around in some of the examples repositories
and I ran across two macro scripts which, together, look like
they might do a density check:
cell_bbox.lym gives the bounding box info for the layout
calc_area_hier.lym gives the total are…
"Real Time DRC" is a feature that many of the big name tools
mention. Also interesting is "guided path" which will route a
path (or bundle) alongside indicated objects, at minimum
distance.
I do find the real time DRC useful wh…
It would seem to me that this particular situation would
be solved by "permute parallel" (aka "device reduction")
MOSFET rules, as the decoupling caps are all entirely parallel?
Should "decompose" into one MOSFET (cap…
Evidently klayout likes strict GDS format compatibility even
in things like byte-counts of fixed format fields. Other tools
may have some "checking and healing" features that let this
kind of thing slide, and reformat the output with prope…
I wonder whether this has to do with the Default font not
being scalable, while the ones in the list are. Can you change
the font property to (say) "Stick" and see if that helps?
I note that the font is not an accessible Property, has t…
You know, I used to get a lot of mileage out of Cadence's
classical graphical PCells (which were perfectly capable
for simple W, L, M kinds of variations). But coding, I have no
abilities (and not much motivation to step away from circuit
design a…
I will observe that the schematic example posted by Matthias
contains an error, in its assertion that the two forms are equivalent.
They are not, unless you add a connection between the left and
right "drain nodes" of the left-hand circui…
For analog circuits where matching is an interest, it would be better to check explicitly all three params (W, L, M) because edge effects make W=2 M=1 different than W=1 M=2 depending on lithography. There are also capacitance concerns for the RF fo…
In a current project the foundry CAD folks directed me to
use zero width paths for my "guide line" features (like, I
place 45'd zero width paths at the edges of the routing
channel drawn through the stretched collector region of
a NPN, to…
It might be that this is a specific permissions thing, that
could be fixed without requiring admin privileges (and
the risk that entails).
There is also a switch setting for read-only vs editable
mode, on file open. Setup>Application>Editing…
This would be interesting to see fitted up to the other related
boundary advice I received in this thread:
https://www.klayout.de/forum/discussion/1423/boolean-operators#latest
I would prefer to let the layout "declare its own size", as …
Some design systems create a pin label, but pin connectivity is taken from the pin object property list and the label is just for the user's convenience. The label is often offset from the box / polygon object and often on another layer (like "…
Thanks, Matthias,
My technology does not have a "boundary" / "bulk" layer but maybe I can fake it.
Am I correct that the "NOT" logic is really "ANDNOT"?
Specifically I have one derived layer that is not-a & not-b & not-c - how can I ANDNOT them all when there's no "positive logic" item to subtract (ANDNOT) from?
Looks like it's got everything that I come to the forum for, and a bit more "marketing friendly" look to it (for whatever that's worth).
I am getting a lot of Firefox "invalid certificate" / "expired certificate" warni…
I know some schematic tools offer options of hierarchical or flat netlist (which would go through and evaluate all of the include-chain). Is this an option for your circuit source?
I haven't found how to get the flat netlist out of simulators like …
Hi, Matthias,
In our (mumblemumble) annular device PCells and extraction, we had some trouble dealing with the gate stub that projects from the core "donut". In fact we gave up on getting great accuracy and just tolerate the error for ab…
Thanks, Matthias,
All I know is, I signed a NDA and the foundry is concerned about preserving their process IP (despite that they've bought the fab from its previous owner and the technology in question is as standard as "standard linear bipol…
I use 7zip but always choose .zip, maximum compression for universal compatibility. I see little difference between .7z and .zip filesizes so have no motivation to "be special".
Then again I do not open layouts from, or try to save into, …