dick_freebird
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I actually use rounded end paths, not that it'd kill me to use square; it's just bond diagram cuteness. My chip design was 89kB, next might be double that so for now, compactness and rendering aren't big deals. Would it be correct to say that a GD…
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I imagine you'd open NewCell as top, then place an instance of OtherCell (specify coords) in the layout. How that looks in Python, no idea.
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Interesting. I have never considered leaving GDS-II format (I work on small ICs generally). Are there any issues with, say, starting a design in GDS-II and trying to move over to OASIS? Lose any data in a conversion or pick up a whole case of empt…
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I think I recall seeing some "checkboxes" to control how the macro windows display / act. Either in File>Setup or under Technology?
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This sounds like the extraction has worked at the lowest level, yielding a correct number of FETs (one per finger)? Then the chore of combining them to a single multifinger falls to either an intermediate "netlist optimizer" or this is …
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Maybe step back a couple, and show what -does- result. Like, no "device" at all, or a herd of small ones where you wanted one representing all fingers? Maybe modify your rules deck to spit out to "debug layers" any layer Boole…
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Why is your L negative? That's the problem. Now given that coords are 32-bit fixed in DBU, might you be using a too-small DBU and a too-long resistor body such that you "wrap around" to 2's complement negative sign, just by bits? Now…
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The "permuteParallel" is one of the topology-massaging rule options in "Brand X" LVS (they shall not be named). A netlist "refinement" stage precedes the connectivity verification, or mops up after (I dunno, a CAD dev…
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"Shape", OK, but that doesn't look like a fully formed MOSFET. If green is Active then where's the gate? If green is gate, where is well(s), active, etc.? Depending on the extract function's code & settings, you might expect to see a…
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I imagine this might be something like a location that's not in the default search path, and maybe said default being overridden by the install process? That's not uncommon in the wider software world, sometimes you need to re-feather your nest …
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There's no real use for a DBU that's smaller than the finest mask spot size, in my book. Look at the foundry's template mask fab order form and you should see guidance in the fracture / spot size columns, with some variation according to layer ge…
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Might be able to do this in a few steps like * turn on deep selection (all levels) * all layers visible / valid * select all * turn off layers you want to keep * area-deselect the region you want to keep * delete * turn on all layers, just what you…
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I have not noticed (in GUI use) any significant wall time for saving entire layout. Maybe two seconds to load and paint at 4K, a full wafer layout from disc (4", 4um feature size, but still - these are fully functioning IC process and circu…
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That's a good tip, thanks. I did find that I could "copy" a layer window entry and "paste" it up top (creating two, same-named) and then deleting the old one from its original position. But that seems error-prone at best, and…
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Thanks, Matthias, By (Quote) do you mean "order in which they appear in the .lyp", "order they appear in the layers window" (maybe the same?) or ??? I see now how to make the tab, it's created a duplicate. But the "sort…
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Wondering whether this is just the hierarchy display being set to "top level only", while a PCell's detail may be one level down? Display > Full Hierarchy ?
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If it were my machine to administer, I would either create these literally, or create symbolic links at these locations pointing to wherever you really intend to keep their "twins" (usr/local/bin?). Seems to me like /usr/bin isn't much (…
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Suspect that this pertains to polygon objects sharing the same level of hierarchy? Or, needs the "deep" selection mode turned back on (but that might get real messy)?
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Not sure this is practical given the GDSII format, but in "Brand X" you can place texts in a layout which will be evaluated and display that evaluated result. One option being something like [%instName] (I'd have to get back to a job wher…
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Don't take my word for what's possible or practical. Only what I've seen, and what I'd like to see. I imagine that a smart guy could code up a script to perform a "masked select" and then it would be easy (I'm told) to add it to your pri…
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I take it that these are "post fab" RDL features, then? I worked at an RFIC company for a while, they used RDL copper for some products. The CAD group had to add these layers to the basic foundry layer set in order that the designers c…
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This is something I've been interested in. My thinking has more revolved around the selection process and how to make it "maskable". But this could take several forms. You could add a "lock position", "lock properties"…
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Not only will they be connected, but this layout would violate basic layout rules. Specifically, via must stop on metal below, else you will etch further into lower interlevel / field dielectric. You will have a fight on your hands, when you get to…
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When I say "baby Caliber", that's a limited version which was bundled with Tanner L-Edit. Later on a more capable (and much, much more expensive) version became part of the Mentor / Synopsys tools set, proved itself more capable of very l…
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I don't know about "big boy" Caliber, but I have been provided Caliber DRC output that's near human readable (if you like mangled English and raw coords / arbitrary device & node naming) from a foundry that uses the "Lite" …
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That's all the way to the bottom of the turtle-pond, yep. Turtles, turtles, turtles. Please post your work once you get it solved so the less (or not at all) clueful among us, can get some traction.
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OP mentions vaguely that there's already a method. What attempt so far, to replicate that method in the "custom device extractor" way? My points have been generally, that there is not a general agreement on even an always-rectilinear form…
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You'd first need to be able to assign terminals and figure a direction between them (L) and orthogonal (W). Same as a thin film resistor I expect. But capacitors I have seen (and drawn) tend to be direction agnostic - MIM caps are nothing but plat…
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If you're not modeling series R then it's a "don't care". Asking for W and L presumes a rectangular form. I am used to seeing "free-form" capacitors in analog IC design (older vintage) and I'd just be taking the thin oxide * top …
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I still don't see addressed, my question whether ".klayout/pymacros" (3rd post) is (1) normal / proper, (2) a valid search path entry. Might suggest trying to invoke these "missing" scripts by full path and see whether it's find…