dick_freebird
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I'll address the segments individually since it was long to begin with... Regarding the topics: (Quote) My "issues" are really with instances. Polygons, you can see what you are getting. Instances, you can select even on "white spac…
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I do not know, but I long for a graphical PCell editor like C*dence Edge. That would be an avenue like you seek.
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It would be great if you could make a "cheat sheet" for a quick leg up on the setup and invocation, and more of a "problems & solutions" reportage that tells what you encountered, how it manifested and how you solved it. W…
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My understanding is that any layer would do, even one you make up yourself for no other purpose. But technologies developed with a major CAD vendor (or according to their normal practices) will probably have a "bulk" or similar "val…
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In that reference I see a couple of things. One is that a basic dual-layer patterning -can- be done the hard way by the designer (who should then know the algorithm, and presumably might be able to script some assistive tools). Another is that fanc…
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I don't know what this means and I'm a semiconductor "lifer" (though never below 12nm/14nm) , so maybe explain a bit more - is this just more "purpose" sub-layers, some sort of secondary layer, or just display fill codes? Just b…
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I've never seen, but never looked for one. A lot of my work ends up on "pizza masks" where multiple dice of different content share a reticle. So I will make the reticle arrangement first. Then there aren't that many steps to fill the s…
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I don't have any experience-based advice (actually hoping to see you "plow the road" with this kind of stuff, ending at some sort of cookbook). But I have glanced at some tutorials laying about, that seemed to offer a primer. Have you d…
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Have you verified that your layout DBU(s) and the script's pixel scaling are in sync? That the "converted" GDS file and your working GDS have identical DBU settings?
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PCells (I believe) display "results of an evaluation" and are not polygons - unless you flatten those instances to "freeze" their evaulation. Might want to copy the present layout to some sandbox and flatten all levels, if there…
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Use the layer window "valid" filter - make all invalid, then make valid the one you want, then you can use "all" or "area" select. You can also decide whether you want to do this at the present level, or deeper. How t…
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If you add all the package construction layers and their "connects", and same for the bond wire, then you can do an end-end / top-bottom verification. Most IC CAD PDKs are single-process and nothing for packaging besides (if you're lucky…
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If you have the data but it's not hooked up: Tools>Manage Technologies If you don't have the library data then hit up Skywater or one of the open source fan clubs that surround the foundry.
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The way I see it, this is about making the parameter comparison for a topoloy-matched device incorporate an "error band" rather than demanding strict numerical equality. Now if PCell:symbol properties 1:1 enforces that matchup, then the…
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That is a peculiar looking Java file and I wonder if it's a "legacy" from a GloFo kit. Might go to the root of the PDK and search for *.json, see what -does- turn up where, maybe there's really a sky130.json that's just waiting for an inv…
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klayout does have the PCells and I believe your problem lies with the scripts which turn properties into polygons - evidently either absent, or someplace that klayout has not been told to look. Scripts have "paths-to". I'd first pore over…
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I would go to the source and pull all the setup info you can find. There should be orderly docs for that as it purports to be a fully capable PDK. But expect "some assembly required", for which there ought to be instructions (or maybe th…
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Yes, I often see subcircuits "wrapping" a MOSFET core element - RF CMOS, see Rg, Ls, Ld added external to the intrinsic FET; ESD GGNMOS clamps work a lot more realistically when you add a breakdown element that BSIM lacks (trivial D mode…
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In my opinion a "parametric" circuit is not verifiable because it's not "done" - it's subject to change until all variables have become fixed. I don't know that this is something worth trying to support. Maybe just as far as co…
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Could you perhaps post a little write-up on your findings, similar to other recent LVS-fail and -solution threads? I think collecting "syndromes" and "cures" is valuable (worthy of collection to the examples-pile, even. Maybe wi…
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I don't know about netlist import here, but if you use ngspice there are args to the 'listing' command which can put you out a fully expanded netlist, even as far as turning any variables into numerical values (like in case you left a FET's W as a …
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Not knowing anything, I'd ask whether there is a pattern of highlighting the "not full ortho width" regions of the via (width done on Cartesian basis, maybe doesn't play with round objects?) but calling the cardinal "flat edges"…
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Well, let's dial it back to the most basic - what about "just" making a "masked select" (point, area, all) function which could sit alongside the existing, but do that one thing? While leaving the as-was selection code and what …
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But still, I believe we do not know why the symmetric-MOS version fails to match? Seems like if force-assigning terminals (DMOS) works then one of the MOS permutes should have satisfied similarly, and been accepted. Am I missing some resolution t…
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I'm thinking that this goes to the "selection process" and any old layer/purpose pair would do (although for general Brand X compatibility I'd default to named "instance/drawing" absent any overriding declaration of "select…
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I would still like to get to a "masked selectability" behavior / feature similar to how Brand X used the instance/drawing layer (until recently - I have been seeing PDKs where this is damaged by the instance/drawing layer being inactivate…
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Yes, they should be but evidently are not, and I am wanting to get to the bottom of "why?". I figure maybe removing known "not-right" from input netlists might help expose the unknown. Which thus far, remains unknown. Let me …
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I disagree that "the schematic netlist is correct". I would go along as far as "it works". But if you inspect the symbols' wiring and the netlist, there is the fact that (for example) M_m6 drain and source are swapped in the net…
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That's good to know. I'm trying to understand why what should work, does not. Because there's a lot of use for symmetric MOS. Provided it's verifiable. Need to know why this is failing, so as not to.
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Given this, I would again suggest that the MOS schematic elements be flipped so that D (symbol) is D (SPICE) and see what results. If the compare "gets right" then the D-S swapping must be somehow compromised. If it makes no difference t…